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1 ltc1707 high efficiency monolithic synchronous step-down switching regulator figure 1b. efficiency vs output load current 22 f 16v 47pf v in * 3v to 8.5v 1707 f01a 6 2 7 1 5 8 3 sw v ref v fb v in run sync/mode i th ltc1707 + 15 h 100 f 6.3v 80.6k *v out follows v in for 3v < vin < 3.3v 249k v out 3.3v + gnd 4 output current (ma) 1 70 efficiency (%) 90 95 100 10 100 1000 1707 f01b 85 80 75 v out = 3.3v v in = 6v v in = 3.6v v in = 8.4v figure 1a. high efficiency low dropout step-down converter the ltc ? 1707 is a high efficiency monolithic current mode synchronous buck regulator using a fixed frequency architecture. the operating supply range is from 8.5v down to 2.85v, making it suitable for both single and dual lithium-ion battery-powered applications. burst mode op- eration provides high efficiency at low load currents. 100% duty cycle provides low dropout operation, extend- ing operating time in battery-powered systems. the switching frequency is internally set at 350khz, allowing the use of small surface mount inductors. for noise sensitive applications it can be externally synchro- nized up to 550khz. burst mode operation is inhibited during synchronization or when the sync/mode pin is pulled low preventing low frequency ripple from interfer- ing with audio circuitry. soft-start is provided by an external capacitor. the internal synchronous mosfet switch increases effi- ciency and eliminates the need for an external schottky diode, saving components and board space. low output voltages down to 0.8v are easily achieved due to the 0.8v internal reference. the ltc1707 comes in an 8-lead so package. n 600ma output current (v in 3 4v) n high efficiency: up to 96% n constant frequency: 350khz synchronizable to 550khz n 2.85v to 8.5v v in range n 0.8v feedback reference allows low voltage outputs: 0.8v v out v in n no schottky diode required n 1.19v 1% reference output pin n selectable burst mode tm operation/pulse skipping mode n low dropout operation: 100% duty cycle n precision 2.7v undervoltage lockout n current mode control for excellent line and load transient response n low quiescent current: 200 m a n shutdown mode draws only 11 m a supply current n available in 8-lead so package , ltc and lt are registered trademarks of linear technology corporation. burst mode is a trademark of linear technology corporation. n cellular telephones n portable instruments n wireless modems n rf communications n distributed power systems n single and dual cell lithium features descriptio u applicatio s u typical applicatio u
2 ltc1707 order part number s8 part marking consult factory for military grade parts. 1707 1707i ltc1707cs8 ltc1707is8 t jmax = 125 c, q ja = 120 c/ w top view v ref sync/mode v in sw i th run/ss v fb gnd s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 (note 1) input supply voltage ................................ C 0.3v to 10v i th voltage ................................................. C 0.3v to 5v run/ss, v fb voltages ............................... C 0.3v to v in sync/mode voltage ................................. C 0.3v to v in p-channel switch source current (dc) .............. 800ma n-channel switch sink current (dc) .................. 800ma peak sw sink and source current ......................... 1.5a operating ambient temperature range commercial ............................................ 0 c to 70 c industrial ........................................... C 40 c to 85 c junction temperature (note 2) ............................. 125 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c symbol parameter conditions min typ max units i vfb feedback current (note 3) 6 60 na v fb regulated feedback voltage (note 3) l 0.78 0.80 0.82 v d v ovl output overvoltage lockout d v ovl = v ovl C v fb 20 60 110 mv d v fb reference voltage line regulation v in = 3v to 8.5v (note 3) 0.002 0.01 %/v v loadreg output voltage load regulation i th sinking 2 m a (note 3) 0.5 0.8 % i th sourcing 2 m a (note 3) C 0.5 C 0.8 % i s input dc bias current (note 4) pulse skipping mode v in = 8.5v, v out = 3.3v, v sync/mode = 0v 300 m a burst mode operation v ith = 0v, v in = 8.5v, v sync/mode = open 200 320 m a shutdown v run/ss = 0v, 3v < v in < 8.5v 11 35 m a shutdown v run/ss = 0v, v in < 3v 6 m a v run/ss run/ss threshold v run/ss ramping positive 0.4 0.7 1.0 v i run/ss soft-start current source v run/ss = 0v 1.2 2.25 3.3 m a i sync/mode sync/mode pull-up current v sync/mode = 0v 0.5 1.5 2.5 m a f osc oscillator frequency v fb = 0.7v 315 350 385 khz v fb = 0v 35 khz v uvlo undervoltage lockout v in ramping down from 3v (0 c to 70 c) 2.55 2.70 2.85 v v in ramping up from 0v (0 c to 70 c) 2.60 2.80 3.00 v v in ramping down from 3v (C40 c to 85 c) 2.45 2.70 2.85 v v in ramping up from 0v (C40 c to 85 c) 2.50 2.80 3.00 v r pfet r ds(on) of p-channel fet i sw = C100ma 0.5 0.7 w r nfet r ds(on) of n-channel fet i sw = C 100ma 0.6 0.8 w i pk peak inductor current v in = 4v, i th = 1.4v, duty cycle < 40% 0.70 0.915 1.10 a i lsw sw leakage v run/ss = 0v 10 1000 na v ref reference output voltage i ref = 0 m a l 1.178 1.19 1.202 mv d v ref reference output load regulation 0v i ref 100 m a l 2.3 15 mv note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 110 c/w) note 3 : the ltc1707 is tested in a feedback loop that servos v fb to the balance point for the error amplifier (v ith = 0.8v). note 4: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 5v unless otherwise specified. absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics
3 ltc1707 efficiency vs input voltage input voltage (v) 0 efficiency (%) 90 95 100 8 1707 g01 85 80 75 2 4 6 10 v out = 2.5v l = 15 m h burst mode operation i load = 100ma i load = 300ma i load = 10ma output current (ma) 1 70 65 60 55 50 efficiency (%) 90 95 100 10 100 1000 1707 g02 85 80 75 burst mode operation pulse skipping mode v in = 3.6v v out = 2.5v l = 15 m h output current (ma) 1 70 efficiency (%) 90 95 100 10 100 1000 1707 g03 85 80 75 v out = 2.5v l = 15 m h burst mode operation v in = 2.8v v in = 3.6v v in = 7.2v efficiency vs load current efficiency vs load current undervoltage lockout threshold vs temperature temperature ( c) ?0 25 2.50 2.55 undervoltage lockout threshold (v) 2.60 2.70 2.75 2.80 75 100 3.00 1707 g04 2.65 0 25 50 125 2.85 2.90 2.95 v in ramping up v in ramping down dc supply current vs input voltage input voltage (v) 2.5 dc supply current ( a) 50 100 150 6.5 350 1707 g05 0 4.5 3.5 7.5 5.5 8.5 200 250 300 t j = 25 c v out = 1.8v load current = 0a burst mode operation pulse skipping mode supply current in shutdown vs input voltage input voltage (v) 2.5 4 supply current in shutdown ( m a) 6 10 12 14 6.5 22 1707 g06 8 4.5 3.5 7.5 5.5 8.5 16 18 20 v run/ss = 0v t j = 85 c t j = 25 c t j = 40 c reference voltage vs temperature oscillator frequency vs temperature temperature ( c) ?0 25 1.180 reference voltage (v) 1.185 1.190 75 100 1.200 1707 g07 0 25 50 125 1.195 v in = 5v oscillator frequency vs input voltage temperature ( c) ?0 25 300 oscillator frequency (khz) 310 330 340 350 75 100 390 1707 g08 320 0 25 50 125 360 370 380 v in = 5v input voltage (v) 2.5 300 oscillator frequency (khz) 310 330 340 350 6.5 390 1627 g09 320 4.5 3.5 7.5 5.5 8.5 360 370 380 typical perfor a ce characteristics uw
4 ltc1707 maximum output current vs input voltage switch leakage current vs temperature switch resistance vs input voltage load step transient response input voltage (v) 2.5 0 output current (ma) 200 400 600 6.5 1000 1707 g10 4.5 3.5 7.5 5.5 8.5 800 t j = 85 c l = 15 m h v out = 5v v out = 1.5v v out = 2.5v v out = 2.9v v out = 3.3v v out = 1.8v temperature ( c) ?0 25 0 switch leakage (na) 200 600 800 1000 75 100 1800 1707 g11 400 0 25 50 125 1200 1400 1600 v in = 8.4v synchronous switch main switch switch resistance vs temperature temperature ( c) ?0 25 0 switch resistance ( w ) 0.1 0.3 0.4 0.5 75 100 0.9 1707 g12 0.2 0 25 50 125 0.6 0.7 0.8 v in = 5v synchronous switch main switch burst mode operation input voltage (v) 2.5 0 switch resistance ( w ) 0.1 0.3 0.4 0.5 6.5 0.9 1707 g13 0.2 4.5 3.5 7.5 5.5 8.5 0.6 0.7 0.8 synchronous switch main switch i th 0.5v/div v out 50mv/div ac coupled i load 500ma/div 25 m s/div 1707 g14 sw 5v/div v out 20mv/div ac coupled i load 200ma/div 10 m s/div 1707 g15 v in = 5v v out = 3.3v l = 15 m h c in = 22 m f c out = 100 m f i load = 0ma to 500ma burst mode operation typical perfor a ce characteristics uw v in = 5v v out = 3.3v l = 15 m h c in = 22 m f c out = 100 m f i load = 50ma
5 ltc1707 i th (pin 1): error amplifier compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is 0v to 1.2v. run/ss (pin 2): combination of soft-start and run control inputs. a capacitor to ground at this pin sets the ramp time to full current output. the time is approximately 0.5s/ m f. forcing this pin below 0.4v shuts down the ltc1707. v fb (pin 3): feedback pin. receives the feedback voltage from an external resistive divider across the output. gnd (pin 4): ground pin. sw (pin 5): switch node connection to inductor. this pin connects to the drains of the internal main and synchro- nous power mosfet switches. v in (pin 6): main supply pin. must be closely decoupled to gnd, pin 4. sync/mode (pin 7): this pin performs two functions: 1) synchronize with an external clock and 2) select be- tween two modes of low load current operation. to synchronize with an external clock, apply a ttl/cmos compatible clock with a frequency between 385khz and 550khz. to select burst mode operation, float the pin or tie it to v in . grounding pin 7 forces pulse skipping mode operation. v ref (pin 8): the output of a 1.19v 1% precision reference. may be loaded up to 100 m a and is stable with up to 2000pf load capacitance. v fb v in 3 v ref 2 1 6 5 4 q q r s 0.12v switching logic and blanking circuit 0.6v i th run/ss 0.8v 0.4v 0.86v sync/mode y = ??only when x is a constant ?? shutdown sleep 6 1.5 a 2.25 a v in v in v in v in sw gnd 1707 bd v in burst en 7 osc freq shift 1.19v ref uvlo trip = 2.7v y x burst defeat slope comp + ovdet + + + + + ea i comp + i rcmp run/soft start anti- shoot-thru 8 uu u pi fu ctio s fu ctio al diagra u u w
6 ltc1707 main control loop the ltc1707 uses a constant frequency, current mode step-down architecture. both the main (p-channel mosfet) and synchronous (n-channel mosfet) switches are internal. during normal operation, the internal top power mosfet is turned on each cycle when the oscillator sets the rs latch, and turned off when the current com- parator, i comp , resets the rs latch. the peak inductor current at which i comp resets the rs latch is controlled by the voltage on the i th pin, which is the output of error amplifier ea. the v fb pin, described in the pin functions section, allows ea to receive an output feedback voltage from an external resistive divider. when the load current increases, it causes a slight decrease in the feedback voltage relative to the 0.8v reference, which, in turn, causes the i th voltage to increase until the average induc- tor current matches the new load current. while the top mosfet is off, the bottom mosfet is turned on until either the inductor current starts to reverse as indicated by the current reversal comparator i rcmp , or the beginning of the next cycle. the main control loop is shut down by pulling the run/ss pin low. releasing run/ss allows an internal 2.25 m a current source to charge soft-start capacitor c ss . when c ss reaches 0.7v, the main control loop is enabled with the i th voltage clamped at approximately 5% of its maximum value. as c ss continues to charge, i th is gradually released, allowing normal operation to resume. comparator ovdet guards against transient overshoots > 7.5% by turning the main switch off and keeping it off until the fault is removed. burst mode operation the ltc1707 is capable of burst mode operation in which the internal power mosfets operate intermittently based on load demand. to enable burst mode operation, simply allow the sync/mode pin to float or connect it to a logic high. to disable burst mode operation and enable pulse skipping mode, connect the sync/mode pin to gnd. in this mode, efficiency is lower at light loads, but becomes comparable to burst mode operation when the output load exceeds 30ma. when the converter is in burst mode operation, the peak current of the inductor is set to approximately 200ma, even though the voltage at the i th pin indicates a lower value. the voltage at the i th pin drops when the inductors average current is greater than the load requirement. as the i th voltage drops below 0.12v, the burst comparator trips, causing the internal sleep line to go high and forcing off both internal power mosfets. in sleep mode, both power mosfets are held off and the internal circuitry is partially turned off, reducing the quies- cent current to 200 m a. the load current is now being supplied from the output capacitor. when the output voltage drops, causing i th to rise above 0.22v, the top mosfet is again turned on and this process repeats. short-circuit protection when the output is shorted to ground, the frequency of the oscillator is reduced to about 35khz, 1/10 the nominal frequency. this frequency foldback ensures that the inductor current has more time to decay, thereby prevent- ing runaway. the oscillators frequency will progressively increase to 350khz (or the synchronized frequency) when v fb rises above 0.3v. frequency synchronization the ltc1707 can be synchronized with an external ttl/cmos compatible clock signal with an amplitude of at least 2v p-p . the frequency range of this signal must be from 385khz to 550khz. do not attempt to synchronize the ltc1707 below 385khz as this may cause abnormal operation and an undesired frequency spectrum. the top mosfet turn-on follows the rising edge of the external source. when the ltc1707 is synchronized to an external source, the ltc1707 operates in pwm pulse skipping mode. in this mode, when the output load is very low, current comparator i comp remains tripped for more than one cycle and forces the main switch to stay off for the same number of cycles. increasing the output load slightly allows con- stant frequency pwm operation to resume. this mode exhibits low output ripple as well as low audio noise and reduced rf interference while providing reasonable low current efficiency. (refer to functional diagram) operatio u
7 ltc1707 frequency synchronization is inhibited when the feedback voltage v fb is below 0.6v. this prevents the external clock from interfering with the frequency foldback for short- circuit protection. dropout operation when the input supply voltage decreases toward the out- put voltage, the duty cycle increases toward the maximum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the p-channel mosfet and the inductor. in burst mode operation or pulse skipping mode operation with the output lightly loaded, the ltc1707 transitions through continuous mode as it enters dropout. undervoltage lockout a precision undervoltage lockout shuts down the ltc1707 when v in drops below 2.7v, making it ideal for single lithium-ion battery applications. in lockout, the ltc1707 draws only several microamperes, which is low enough to prevent deep discharge and possible damage to the lithium- ion battery nearing its end of charge. a 100mv hysteresis ensures reliable operation with noisy input supplies. low supply operation the ltc1707 is designed to operate down to a 2.85v input voltage. at this voltage the converter is most likely to be running at high duty cycles or in dropout where the main switch is on continuously. hence, the i 2 r loss is due mainly to the r ds(on) of the p-channel mosfet. see efficiency considerations in the applications information section. below v in = 4v, the output current must be derated as shown in figures 2a and 2b. for applications that require 500ma below v in = 4v, select the ltc1627. figure 2a. maximum output current vs input voltage (unsynchronized) input voltage (v) 2.5 0 output current (ma) 200 400 600 6.5 1200 1000 1707 f02a 4.5 3.5 7.5 5.5 8.5 800 t j = 25 c l = 15 m h v out = 5v v out = 1.5v v out = 2.5v v out = 2.9v v out = 3.3v v out = 1.8v input voltage (v) 2.5 0 output current (ma) 200 400 600 6.5 1200 1000 1707 f02b 4.5 3.5 7.5 5.5 8.5 800 t j = 25 c l = 15 m h ext sync at 400khz v out = 5v v out = 1.5v v out = 2.9v v out = 3.3v v out = 1.8v v out = 2.5v figure 2b. maximum output current vs input voltage (synchronized) figure 3. maximum inductor peak current vs duty cycle 0 10 20 30 40 50 60 70 80 90 100 1000 900 800 700 600 500 duty cycle (%) 1707 f03 maximum inductor peak current (ma) worst-case external clock sync without external clock sync v in = 4v slope compensation and inductor peak current slope compensation provides stability by preventing sub- harmonic oscillations. it works by internally adding a ramp to the inductor current signal at duty cycles in excess of 40%. as a result, the maximum inductor peak current is lower for v out /v in > 0.4 than when v out /v in < 0.4. see the inductor peak current as a function of duty cycle graph in figure 3. the worst-case peak current reduction occurs operatio u
8 ltc1707 with the oscillator synchronized at its minimum frequency, i.e., to a clock just above the oscillator free-running frequency. the actual reduction in average current is less than for peak current. the basic ltc1707 application circuit is shown in figure 1a. external component selection is driven by the load re- quirement and begins with the selection of l followed by c in and c out. inductor value calculation the inductor selection will depend on the operating fre- quency of the ltc1707. the internal preset frequency is 350khz, but can be externally synchronized up to 550khz. the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. however, oper- ating at a higher frequency generally results in lower efficiency because of increased internal gate charge losses. the inductor value has a direct effect on ripple current. the ripple current d i l decreases with higher inductance or frequency and increases with higher v in or v out . d i fl v v v l out out in = ()( ) - ? ? ? ? 1 1 (1) accepting larger values of d i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is d i l = 0.4(i max ). the inductor value also has an effect on burst mode operation. the transition to low current operation begins when the inductor current peaks fall to approximately 200ma. lower inductor values (higher d i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or kool m m ? cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! kool m m (from magnetics, inc.) is a very good, low loss core material for toroids with a soft saturation character- istic. molypermalloy is slightly more efficient at high (>200khz) switching frequencies but quite a bit more expensive. toroids are very space efficient, especially when you can use several layers of wire, while inductors wound on bobbins are generally easier to surface mount. new designs for surface mount are available from coiltronics, coilcraft and sumida. c in and c out selection in continuous mode, the source current of the top mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: ci vvv v in max out in out in required i rms @ - () [] 12 / this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet kool m m is a registered trademark of magnetics, inc. applicatio s i for atio wu uu
9 ltc1707 size or height requirements in the design. always consult the manufacturer if there is any question. the selection of c out is driven by the required effective series resistance (esr). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple d v out is determined by: dd v i esr fc out l out @+ ? ? ? ? 1 8 where f = operating frequency, c out = output capacitance and d i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since d i l increases with input voltage. for the ltc1707, the general rule for proper operation is: c out required esr < 0.25 w manufacturers such as nichicon, united chemicon and sanyo should be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest esr/size ratio of any aluminum electrolytic at a somewhat higher price. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. remember esr is typically a direct function of the volume of the capacitor. in surface mount applications multiple capacitors may have to be paralleled to meet the esr or rms current handling requirements of the application. aluminum electrolytic and dry tantalum capacitors are both avail- able in surface mount configurations. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalum, avail- able in case heights ranging from 2mm to 4mm. other capacitor types include sanyo poscap, kemet t510 figure 4. setting the ltc1707 output voltage run/ss c ss d1 3.3v or 5v c ss run/ss 1707 f05 figure 5. run/ss pin interfacing and t495 series, nichicon pl series and sprague 593d and 595d series. consult the manufacturer for other specific recommendations. output voltage programming the output voltage is set by a resistive divider according to the following formula: vv r r out =+ ? ? ? ? 08 1 2 1 . (2) the external resistive divider is connected to the output, allowing remote voltage sensing as shown in figure 4. run/soft-start function the run/ss pin is a dual purpose pin that provides the soft-start function and a means to shut down the ltc1707. soft-start reduces surge currents from v in by gradually increasing the internal current limit. power supply sequencing can also be accomplished using this pin. an internal 2.25 m a current source charges up an external capacitor c ss . when the voltage on run/ss reaches 0.7v the ltc1707 begins operating. as the voltage on run/ss continues to ramp from 0.7v to 1.8v, the inter- nal current limit is also ramped at a proportional linear rate. the current limit begins at 25ma (at v run/ss 0.7v) and ends at the figure 3 value (v run/ss ? 1.8v). the output current thus ramps up slowly, charging the output capacitor. if run/ss has been pulled all the way to ground, there will be a delay before the current starts increasing and is given by: t c a delay ss = 07 225 . .m pulling the run/ss pin below 0.4v puts the ltc1707 into a low quiescent current shutdown (i q < 15 m a). this pin can be driven directly from logic as shown in figure 5. diode 0.8v v out 8.5v r2 r1 1707 f04 v fb gnd ltc1707 applicatio s i for atio wu uu
10 ltc1707 d1 in figure 5 reduces the start delay but allows c ss to ramp up slowly providing the soft-start function. this diode can be deleted if soft-start is not needed. efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in ltc1707 circuits: v in quiescent current and i 2 r losses. the v in quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in figure 6. 1. the v in quiescent current is due to two components: the dc bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low or from low to high, a packet of charge dq moves from v in to ground. the resulting dq/dt is the current out of v in that is typically larger than the dc bias current. in continuous mode, i gatechg = f(q t + q b ) where q t and q b are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches r sw and external inductor r l . in continuous mode the average output current flowing through inductor l is chopped between the main switch and the synchronous switch. thus, the series resistance looking into sw pin from l is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteris- tics curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply by the square of the average output current. other losses including c in and c out esr dissipative losses, mosfet switching losses and inductor core and copper losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ( d i load ? esr), where esr is the effective series resistance of c out . d i load also begins to charge or dis- charge c out , which generates a feedback error signal. the regulator loop then acts to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the internal compensation provides adequate compensation for most applications. but if additional compensation is required, the i th pin can be used for external compensation as shown in figure 7 (the 47pf capacitor, c c2 , is typically needed for noise decoupling). load current (ma) 1 0.001 power lost (w) 0.01 0.1 1 10 100 1000 1707 f06 v out = 1.5v v out = 3.3v v out = 5v v in = 6v figure 6. power lost vs load current applicatio s i for atio wu uu
11 ltc1707 a second, more severe transient is caused by switching in loads with large (>1 m f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 ? c load ). thus, a 10 m f capacitor charging to 3.3v would require a 250 m s rise time, limiting the charging current to about 130ma. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1707. these items are also illustrated graphically in the layout diagram of figure 7. check the following in your layout: 1. are the signal and power grounds segregated? the ltc1707 signal ground consists of the resistive divider, the optional compensation network (r c and c c1 ), c ss , c ref and c c2 . the power ground consists of the (C) plate of c in , the (C) plate of c out and pin 4 of the ltc1707. the power ground traces should be kept short, direct and wide. the signal ground and power ground should converge to a common node in a star- ground configuration. 2. does the v fb pin connect directly to the feedback resistors? the resistive divider r1/r2 must be con- nected between the (+) plate of c out and signal ground. 3. does the (+) plate of c in connect to v in as closely as possible? this capacitor provides the ac current to the internal power mosfets. 4. keep the switching node sw away from sensitive small- signal nodes. figure 7. ltc1707 layout diagram c c2 c c1 r c optional c ss c out c in l1 r1 bold lines indicate high current paths 1 2 3 4 8 7 6 5 v ref sync/mode v in sw i th run/ss v fb gnd ltc1707 r2 v in 1707 f07 + v out + c ref + + applicatio s i for atio wu uu
12 ltc1707 output current (ma) efficiency (%) 1 100 1000 1707 f08b 10 100 90 80 70 60 50 v out = 2.5v l = 22 h burst mode operation v in = 3.6v v in = 4.2v c ss 0.1 f c out ? 100 f 6.3v c in ?? 22 f 16v 22 h* * sumida cd54-220 ? avx tpsc107m006r0150 ?? avx tpsc226m016r0375 r2 169k 1% r1 80.6k 1% c ith 47pf 1 2 3 4 8 7 6 5 v ref sync/mode v in sw i th run/ss v fb gnd ltc1707 v in 2.85v to 4.5v v out 2.5v 0.3a 1707 f08a + + figure 8. single lithium-ion to 2.5v/0.3a regulator from design example design example as a design example, assume the ltc1707 is used in a single lithium-ion battery-powered cellular phone applica- tion. the v in will be operating from a maximum of 4.2v down to about 2.85v. the load current requirement is a maximum of 0.3a but most of the time it will be in standby mode, requiring only 2ma. efficiency at both low and high load currents is important. output voltage is 2.5v. with this information we can calculate l using equation (1), l fi v v v l out out in = ()( ) - ? ? ? ? 1 1 d (3) substituting v out = 2.5v, v in = 4.2v, d i l = 120ma and f = 350khz in equation (3) gives: l v khz ma v v h = ()() - ? ? ? ? = 25 350 120 1 25 42 24 1 .. . . m a 22 m h inductor works well for this application. for best efficiency choose a 1a inductor with less than 0.25 w series resistance. c in will require an rms current rating of at least 0.15a at temperature and c out will require an esr of less than 0.25 w . in most applications, the requirements for these capacitors are fairly similar. for the feedback resistors, choose r1 = 80.6k. r2 can then be calculated from equation (2) to be: r v rk out 2 08 1 1 171 =- ? ? ? ? = . ; use 169k figure 8 shows the complete circuit along with its effi- ciency curve. applicatio s i for atio wu uu
13 ltc1707 double lithium-ion battery to 5v/0.5a low dropout regulator c ith 47pf c ss 0.1 f 33 h* 1 2 3 4 8 7 6 5 v ref sync/mode v in sw i th run/ss v fb gnd ltc1707 v in 8.4v v out 5v 0.5a 1707 ta02 + + c out ** 100 f 10v c in *** 22 f 16v r2 422k 1% r1 80.6k 1% * sumida cd54-330 ** avx tpsd107m010r0100 *** avx tpsc226m016r0375 5v input to 3.3v/0.6a regulator c ith 47pf c ss 0.1 f 15 h* 1 2 3 4 8 7 6 5 v ref sync/mode v in sw i th run/ss v fb gnd ltc1707 v in = 5v v out 3.3v 0.6a 1707 ta01 + c out ** 100 f 6.3v c in *** 10 f ceramic r2 249k 1% r1 80.6k 1% * sumida cd54-150 ** avx tpsc107m006r0150 *** taiyo yuden lmk325bj106k-t typical applicatio s u
14 ltc1707 c ss 0.1 f c out ? 100 f 6.3v c in ** 10 f ceramic 10 h* * sumida cd54-100 ** taiyo yuden lmk325bj106k-t ? avx tpsc107m006r0150 r2 169k 1% r1 80.6k 1% c ith 47pf 1 2 3 4 8 7 6 5 v ref sync/mode v in sw i th run/ss v fb gnd ltc1707 v in = 3.3v v out 2.5v 0.4a 1707 ta03 + 3.3v input to 2.5v/0.4a regulator double lithium-ion to 2.5v/0.5a regulator c ith 47pf c ss 0.1 f 25 h* 1 2 3 4 8 7 6 5 v ref sync/mode v in sw i th run/ss v fb gnd ltc1707 v in 8.4v v out 2.5v 0.5a 1707 ta05 + + c out ** 100 f 6.3v c in *** 22 f 16v r2 169k 1% r1 80.6k 1% * sumida cd54-250 ** avx tpsc107m006r0150 *** avx tpsc226m016r0375 typical applicatio s u
15 ltc1707 dimensions in inches (millimeters) unless otherwise noted. s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 1298 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16 ltc1707 1707f lt/tp 0600 4k ? printed in usa ? linear technology corporation 1999 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com single lithium-ion to 1.8v/0.3a regulator related parts part number description comments ltc1174/ltc1174-3.3 high efficiency step-down and inverting dc/dc converters monolithic switching regulators, i out to 450ma, ltc1174-5 burst mode operation ltc1265 1.2a, high efficiency step-down dc/dc converter constant off-time, monolithic, burst mode operation lt ? 1375/lt1376 1.5a, 500khz step-down switching regulators high frequency, small inductor, high efficiency ltc1436a/ltc1436a-pll high efficiency, low noise, synchronous step-down converters 24-pin narrow ssop ltc1474/ltc1475 low quiescent current step-down dc/dc converters monolithic, i out to 250ma, i q = 10 m a, 8-pin msop ltc1504a monolithic synchronous step-down switching regulator low cost, voltage mode i out to 500ma, v in from 4v to 10v ltc1622 low input voltage current mode step-down dc/dc controller 550khz constant frequency, external p-channel switch, i out to 4a, v in from 2v to 10v ltc1626 low voltage, high efficiency step-down dc/dc converter monolithic, constant off-time, i out to 600ma, low supply voltage range: 2.5v to 6v ltc1627 monolithic synchronous step-down switching regulator constant frequency, i out to 500ma, secondary winding regulation, v in from 2.65v to 8.5v ltc1701 monolithic current mode step-down switching regulator constant off-time, i out to 500ma, 1mhz operation, v in from 2.5v to 5.5v ltc1735 high efficiency, synchronous step-down converter 16-pin so and ssop, v in up to 36v, fault protection ltc1772 low input voltage current mode step-down dc/dc controller 550khz, 6-pin sot-23, i out up to 5a, v in from 2.2v to 10v ltc1877 high efficiency monolithic step-down regulator 550khz, ms8, v in up to 10v, i q = 10 m a, i out to 600ma ltc1878 high efficiency monolithic step-down regulator 550khz, ms8, v in up to 6v, i q = 10 m a, i out to 600ma c ith 47pf c ss 0.1 f 15 h* 1 2 3 4 8 7 6 5 v ref sync/mode v in sw i th run/ss v fb gnd ltc1707 v in 4.2v v out 1.8v 0.3a 1707 ta04 + c out ** 100 f 6.3v c in *** 10 f ceramic r2 100k 1% r1 80.6k 1% * sumida cd54-150 ** avx tpsc107m006r0150 *** taiyo yuden lmk325bj106k-t typical applicatio u

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